In multi-GHz chip design domains, interconnects are becoming the limiting factor in the performance, energy dissipation, and signal integrity. The demanding requirements from on-chip wiring pose a serious problem, both from the design and the modeling aspects.
Previous solutions for considering on-chip interconnects have focused on analysis of given designs. These include RC(L) extraction methods and analysis tools based on field solvers.
The attempts to develop post-layout RCL extraction methods usually fail to correctly determine the wire inductances, due to the inability to determine the correct current return paths. In addition, existing RC(L) extraction tools do not take into account several physical effects, such as substrate effects, which are expected to have a significant impact on the design performance.
The field solver based analysis tools require the user to define the relevant solution domain including the interconnect to be analyzed, as well as the boundary conditions, for which a deep electromagnetic understanding is needed. As a result, the solution domain can be either redundant or insufficient, or both, which leads to errors that are almost impossible to track.